1. SOC RV1126, Pin ad Pin compatible cum RV1109;

2. DDR3L (Samsung K4B4G1646E BCNB)

A 4G bit DDR3 K4B4G1646E BCNB adnexum est tabulae anteriori et posteriori totius, cum summa 8G frenum DDR3;

3. SPI Nand Flash:

Versione A instructa 2G bit SPI Nand Flash XT26G02AWSEGA

Versione B instructa 4G bit SPI Nand Flash XT26G04AWSEGA

4. RMII PHY (RTL8001F)

5. Codec (ES8311)

6.Transformer (Retiacula solitudo transformer MS10232ANL)

Pin1	VCC5V0_OTG
Pin2	OTG_DM
Pin3	OTG_DP
Pin4	GND

9.Aer&Jack virtute

Pin1	TX+	Pin6	RX-
Pin2	Corpus-	Pin7	POE78
Pin3	RX+	Pin8	POE78
Pin4	POE45	Pin9	GND
Pin5	POE45	Pin10	VCC12V_DCIN

10. Audio Connector

Pin1	LED1/PHYAD1
Pin2	LED0 / PHYAD0
Pin3	RESET
Pin4	MICP
Pin5	GND
Pin6	DE LINEE

Retro View specificationem

1.DDR3L (Samsung K4B4G1646E BCNB)

A 4Gbit DDR3 adnectitur pronao et postico totius tabulae, cum summa 8G bits;

2.MIPI DSI Connector

Pin1	IRQ	Pin11	MIPI_DSI_D3N
Pin2	PWR_EN	Pin12	MIPI_DSI_D3P
Pin3	RST	Pin13	MIPI_DSI_D0N
Pin4	I2C3_SDA	Pin14	MIPI_DSI_D0P
Pin5	I2C3_SCL	Pin15	GND
Pin6	GND	Pin16	MIPI_DSI_CLKN
Pin7	MIPI_DSI_D2P	Pin17	MIPI_DSI_CLKP
Pin8	MIPI_DSI_D2N	Pin18	GND
Pin9	MIPI_DSI_D1P	Pin19	VCC_12V
Pin10	MIPI_DSI_D1N	Pin20	VCC_12V

3.MIPI CSI Connector

Pin1	VCC3V3_SYS	Pin21	MIPI_CSI_RX0_D1N
Pin2	VCC3V3_SYS	Pin22	MIPI_CSI_RX0_D0P
Pin3	SPI0_CLK	Pin23	MIPI_CSI_RX0_D0N
Pin4	LED_PWM	Pin24	GND
Pin5	SPI0_CS0N	Pin25	MIPI_CSI_CLK0
Pin6	SPI0_MISO	Pin26	GND
Pin7	SPI0_MOSI	Pin27	PWM8
Pin8	I2C1_SDA	Pin28	IRC_AIN
Pin9	I2C1_SCL	Pin29	PWM11
Pin10	MIPI_RX0_PDN	Pin30	PWM9
Pin11	MIPI_RX0_RST	Pin31	IRC_BIN
Pin12	GND	Pin32	ZOOM_EN
Pin13	MIPI_CSI_RX0_CLKP	Pin33	PWM10
Pin14	MIPI_CSI_RX0_CLKN	Pin34	P-IRIS_EN
Pin15	GND	Pin35	FOCUS_EN
Pin16	MIPI_CSI_RX0_D2P	Pin36	ADC_IN
Pin17	MIPI_CSI_RX0_D2N	Pin37	GND
Pin18	MIPI_CSI_RX0_D3P	Pin38	VCC_1V8
Pin19	MIPI_CSI_RX0_D3N	Pin39	VCC_12V
Pin20	MIPI_CSI_RX0_D1P	Pin40	VCC_12V

4.Munus Connector

Pin1	HOST_DM	Pin14	SDMMC0_D0
Pin2	HOST_DP	Pin15	SDMMC0_CLK
Pin3	GND	Pin16	SDMMC0_D3
Pin4	GND	Pin17	RS485_CTL
Pin5	ALARM_IN	Pin18	UART3_RX_485
Pin6	SDMMC0_DET	Pin19	UART3_TX_485
Pin7	ALARM_OUT	Pin20	GND
Pin8	SDMMC0_PWREN	Pin21	VCC_12V
Pin9	SDMMC0_D2	Pin22	VCC_12V
Pin10	USB_PWREN	Pin23	POE45
Pin11	SDMMC0_CMD	Pin24	POE78
Pin12	GND	Pin25	POE36
Pin13	SDMMC0_D1	Pin26	POE12

1.1 Overview
RV1126 est summus processus visionis processus SoC pro IPC/CVR, praesertim AI actis applications. Fundatur in nucleo quadrum ARM Cortex A7 32-bit nucleus qui NEON et FPU integratur.. Est 32KB I-cache et 32KB D-cache pro nucleo et 512KB unita L2 cache. Constructum-in NPU sustinet INT8/INT16 operatio hybridarum et computandi potestas est usque ad 2.0TOPs. Autem, fortis convenientiae, exempla retis innixa in serie compagum ut TensorFlow/MXNet/PyTorch/Caffe facile converti possunt.<br>
RV1126 etiam novam inducit generationem prorsus ferramentis fundatam 14-megapixel ISP (imago signum processus) et post processus. Multum algorithm acceleratorium in IPC et CVR adhiberi solet, ut HDR, 3A munera (AE*, OF', AWB), LSC, 3DNR, 2DNR, acuere, dehaze, fisheye disciplinam, gamma correctionis, et sic in pluma puncta deprehendatur. Omnes eorum sunt realis-vicis processus. Adiutricem operam cum duobus MIPI CSI (or LVDS/SubLVDS) et unus DVP (BT.601/BT.656/BT.1120) interface, users potest aedificare ratio quae accipit video notitia ex 3 camera sensors simultaneously.
Video encoder in RV1126 subsidiis UHD H.265/H.264 descriptam esse;. Etiam multi-amnis modum translitterandi sustinet, ad unum 4Kp30 et unum 1080p30 simultaneum. Ope haec factura, video e camera cum resolutione altiori conlocari potest et in memoria locali reposita et ad aliam resolutionem inferiorem simul ad nubem reposita transferri.. H.264/H.265 video decoder in RV1126 subsidiis 4Kp30 pro H.264 et H.265.
In addition to the previous high-perficiendi multimedia scandalum, RV1126 etiam continet dives audio, memoria, et aliae interfaces peripherales ut I2C, SPI, PWM, et sic porro. Hi iuvare possunt utentes plus sensoriis vel aliis periphericis in totum systema addere ad flexibilitatem et expansionem meliorem.
RV1126 has high-perficiendi externum DRAM (DDR3/DDR3L/DDR4/LPDDR3/LPDDR4-2133) sustentare poscentem memoriam bandwidthths.
1.2 Features
Lineamenta infra recensita quae in actu actuali adesse possunt vel non possunt, tertiae parti licentiae requisita subiici possunt.. Please contact Rockchip for actual product feature configurations and licenses requirements ..
1.2.1 Applicationem Processor
Quad-Cortex-A7
ARMO architectura piena institutio v7-, ARM Neon Advanced SIMD
Separatim Integrated Neon et FPU
 32KB L1 I-Cache et 32KB L1 D-cache per Cortex-A7 CPU
Uniated 512KB L2 Cache pro Quad-Corte Cortex-A7
TrustZone technology confirmavit
 Ditiones potentiae separatae pro CPU core systematis ad potentiam internam transibit et exterius conversus in / off fundatur in diversa applicatione sem
PD_CPU0: 1st Cortex-A7 + Neon + FPU + L1 I/D Cache
PD_CPU1: 2nd Cortex-A7 + Neon + FPU + L1 I/D Cache
PD_CPU2: 3rd Cortex-A7 + Neon + FPU + L1 I/D Cache
PD_CPU3: 4th Cortex-A7 + Neon + FPU + L1 I/D Cache
Una intentione secreta domain ad auxilium DVFS
1.2.2 Video input Interface
Interface et video initus processus
Duo MIPI CSI/LVDS/SubLVDS interfaces, 4 vicos quisque, MIPI CSI max data rate est 2.5Gbps/lane, LVDS/SublVDS max data rate est 1Gbps/lane
 Die 8/10/12/16 frenum vexillum DVP interface, ad 150MHz initus data
Support BT.601/BT.656 et BT.1120 VI interfaces
Suscipe verticitatem pixel_clk、hsync、vsync configurable
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
ISP
Maxime resolutio est 14Mpixel(44163312)
DVP input: ITU-R BT.601/656/1120 with raw8/raw10/raw12/raw16, YUV422
MIPI input: RX data lane x1/x2/x4, raw8/raw10/raw12, YUV422
3A: includit AE / Histogram, OF', AWB statistics output
FPN: Certa Exemplum remotionem sonitus
BLC: Nigrum Level Correctio
DPCC: Static / Dynamic defectus pixel botrum emendatio
LSC: Lens colorum correptio
Bayer NO: Bayer-rudis De-sonans, 2DNR
HDR: 3-/2-Artus Merge in High-Dynamic dolor
TMO: 3-/2-Frame Merge Video Tone mapping
WDR: One Frame Wide-Dynamic Range Tone mapping
Debayer: Provectus Adaptive Demosaicus cum Chromatic Aberratio Correctio
CCM/CSM: Color correctionis matrix; RGB2YUV etc.
Gamma: Gamma de correctione
Dehaze / augendae: Lorem Dehaze et in ore amplificationem
3DLUT: 3D-Lut Color Palette ad Customer
LDCH: Lens distortio in directione horizontali
Output Scale *3: support scale in planum * III "(W0&lt;3264; W1&lt;1280; W2&lt;1280)
Output Scale *2: support scale in planum * II "(W0&lt;1920; W1&lt;1920)
Output (FBC): support YUV422/420 cum Frame Buffer Compressione
3DNR: Advanced Temporal Noise Reduction in YUV
2DNR: Advanced Spatial Noise reduction in YUV
Sharp: Picture Sharpening &amp; Ora augendae in YUV
ORB: orientatur Fast et Rotated BREVIS, a method of feature point detection
FEC: maior Lens-tortio et Piscium oculus correctio
CGC: Color Gamut Compressione, YUV plena range / terminus range converto
1.2.3 Vide CODEX
Video Decoder
Real-time decoding of H.264 et H.265
Main and Main10 profile for H.265, ad planum 5.0 and 4096×2304@30fps
Baseline, main, summus, high10 et altum 4:2:2(sine MBAFF), ad planum 5.1 and 4096×2304@30fps
Video Encoder
Real-time UHD H.265/H.264 video modum translitterandi
I-/P- tabulae et SmartP reference ..
 Five-bit rate control modes (CBR, VBR, FixQp, AVBR, et QpMap)
Sursum to 100 Mbit/s output bit rate
Support ROI(non finis) modum translitterandi;
High profile for H.264, ad planum 5.1 and 4096×2304@30fps
Main profile for H.265, ad planum 5.0 and 4096×2304@30fps
Support multi-amnis modum translitterandi
 3840 x 2160@30 fps + 1080p@ XXX fps modum translitterandi
 3840 x 2160@30 descriptam + 3840 x 2160@30 fps decoding
Input data forma:
YCbCr 4:2:0 planae
YCbCr 4:2:0 semi-planaribus
YCBYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 et BGR444
RGB555 et BGR555
RGB565 et BGR565
RGB888 et BRG888
RGB101010 et BRG101010
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
Una intentione secreta domain ad auxilium DVFS
1.2.4 JPEG CODEX
JPEG Encoder
Baseline (DCT sequential)
 Encoder size est ab 96×96 ad 8192×8192(67Mpixels)
Sursum to 90 decies elementa secundo
JPEG Decoder
Decoder amplitudo est ab 48×48 ad 8176×8176(66.8Mpixels)
Sursum to 76 decies elementa secundo
1.2.5 Neural Processus Unit
Neural network accelerationis engine cum processui perficiendi usque ad 2.0 TOPS
Integer Support 8, integer 16 operatio convolutionis
Support penitus cognita compagibus: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Hard, Darknet
Support OpenVX API
Una intentione secreta domain ad auxilium DVFS
1.2.6 Memoria Organization
Internum in-chip memoria
BootRom
 SYSTEM_SRAM in intentione VD_LOGIC
PMU_SRAM in intentione VD_PMU ad applicationem virtutis humilis
Externi extemporalitatis memoria
DDR3/DDR3L/DDR4/LPDDR3/LPDDR4-2133①
SPI Flash
eMMC
SD Card
Async Nand Flash
1.2.7 Internum Memoria
Internum BootRom
Support tabernus ratio ex hoc machinam:
FSPI Flash interface
eMMC interface
SDMMC interface
Async Nand interface
Support ratio codice download ab his interface:
USB OTG interface (Device modus)
SYSTEM_SRAM
Size: 64KB
PMU_SRAM
Size: 8KB
1.2.8 Memoria externa vel repono fabrica
Dynamic Memoria Interface (DDR3/DDR3L/DDR4/LPDDR3/LPDDR4-2133)
Compatible cum JEDEC signis
 Compatible cum DDR3/DDR3L/DDR4/LPDDR3/LPDDR4-2133
Support XXXII frenum notitia width, 2 ordines (chip eligit), max 4GB addressing per spatium gradum, totalis addressing locus est 4GB (max)
Minimum virtutis modos, ut potestate et auto-renovare SDRAM
eMMC Interface
Compatible cum vexillum iNAND interface
Compatible cum eMMC specificationem 4.51
Suscipe tria data bus latitudines: 1-paulum, 4-frenum vel VIII-bit
Suscipe ad HS200; sed non support CMD Queue
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
SD/MMC Interface
Compatible cum SD3.0, MMC ver4.51
Data bus latitudo 4bits
Flexibile Serial Flash interface(FSPI)
Support translatio notitia ex / ut Vide mico fabrica
Support x1, x2, x4 notitia bits modus
Support 2 eu eligere
Nand Flash Interface
Support async nand mico
Data bus latitudo 8bits
Support 1 chip eligere
Support LBA nand flash
Sursum ad 16bits/1KB hardware ECC
Support configurable interface leo
1.2.9 Systema Component
RISC-V MCU
32bit microcontroller core cum RISC -V ISA
Harvard architectura, separatum Instructio, et data memorias
Instructio paro est RV32I cum extensionibus M et C
Integrated Programmable Interrumpere Controller (IPIC), omnis 123 IRQ lineae cum GIC annexae pro Cortex-A7 etiam connectunt cum RISC -V MCU .
Integrated Debug Controller with JTAG interface
CRU (horologium &amp; reset unitas)
Suscipe horologium imperium per singulas partes
unus oscillator cum 24MHz horologium initus
Support global mollis reset imperium pro toto chip, et singula mollis, reset ad invicem component
PMU (potestas procuratio unitatis)
Support 5 disiunctiones intentionis disiunctae VD_CORE/VD_LOGIC/VD_PMU/VD_NPU/VD_VEPU
Support 14 separatum imperium domains, quae potest sursum/down per software fundatur in diversis application scaenarum
 Multiplices configurabiles modi operandi ad servandum potentiam a diversis frequentia vel latis horologii potestatem vel potestatem dominii in / off imperium
Timer
Support 6 64aliquantulus-timers cum interrupt-fundatur operatio pro non-securam applicationem
Support 2 64aliquantulus-timers cum interrupt-fundatur operatio pro secure application
Suscipe duos modos operandi: liberum cursus ac user-defined comitem
Support timor operis status checkable
PWM
Support 12 in-chip PWMs (PWM0 ~ PWM11) cum adjicias, secundum operationem
Programmabile prae-scandebat operationem in horologii bus et deinde ultra scalis
Embedded XXXII frenum timor / contra facility
Support captis modus
Support continui modus vel unus-iecit modus
providet referat modum et outputs variis officium-cyclus waveform
Optimized for IR application pro PWM3, PWM7, et PWM11 "
Watchdog
32-bit vigil counter
In arcu computatur ab consectetur pretium ad 0 ut indicant eventum timeout
WDT duo genera operationum praestare potest cum timeout occurs:
Generate ratio reset
Primum, generare interruptionem et si hoc non purgatur per usitatum ministerium tempore secundo occurrit tunc systema generare
Programmable reset longitudinem pulsus
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
Totaliter 16 definitum iugis pelagus timeout tempus
One Watchdog for non-securam application
One Watchdog for secure application
Interpellare Controller
Support 128 SPI interrumpere fontes initus ex diversis componentibus
Support 16 software, Urguet obloquitur
Duo adjicias outputs (nFIQ et nIRQ*) separatim inter se Cortex-A7, utrumque humili gradu sensitivo
Suscipe diversis potioribus interrumpere pro se fonte adjicias, et semper sunt programmatio programmatum
DMAC
Micro-code programming-fundatur DMA
 Munus coniunctum album DMA sustentatur ad translationem dispertiendam integram
Support notitia translationis genera cum memoria-ad-memoria, memoria ut- periphericis, periphericis ut- memoriam
Signat eventum diversorum DMA eventuum utens interrumpere significationibus output
One embedded DMA controller ad systema
DMAC features:
Support 8 ductus
 27 hardware petitiones peripherals
 2 obloquitur output
 Support TrustZone technology and programmable secure state for each DMA channel
Secure System
Cipher engine
Support SM2/SM3/SM4 cipher
Support HA-1, SHA-256/224, SHA-512/384, et MD5 cum hardware Nullam
Support Link List Item (LLI) DMA translatio
Support AES-128 AES-256 encrypt &amp; minutum cipher
Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS modus
DES support &amp; TDES encrypt &amp; minutum cipher
DES/TDES ECB/CBC/OFB/CFB modus
Support up to 4096 bits PKA res mathematicas ad RSA / ECC *
Support ad VIII-alvei configuratione
Suscipe Sursum to 256 frusta TRNG output
Support notitia ruentes omnibus DDR types
Support secure OTP
Support secure debug
Support secure OS
Mailbox
Una Mailbox in SoC ad servitium A7 et RISC-V MCU communicationis
Suscipe quattuor per mailbox elementis per mailbox, unumquodque elementum includit unum data verbum, unum mandatum verbum mandare, et unum vexillum frenum quod repraesentare possit interrumpunt
Provide 32 cincinno registra pro software uti ad indicandum an in mailbox occupata
LIBERI
Support pro decompressing GZIP files
Support pro decompressing LZ4 files, inter quas structuram generalem LZ4 Frame format et Legacy Frame format.
Support pro decompressing data in Deflate forma
Support pro decompressing data in ZLIB forma
Support completum interrumpere et errorem interrumpere output
Support Hash32 reprehendo in LZ4 decompression process
Suscipe modum magnitudinis functionis decompressed notitia ne memoria in malitiose destruatur in processu decompression
Support software ut prohibere decompression processum
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
1.2.10 Graphics Engine
2D Graphics Engine (RGA):
Source formats:
ABGR8888, XBGR888, ARGB8888, XRGB888
RGB888, RGB565
RGBA5551, RGBA4444
 YUV420 planae, YUV420 semi-planaribus
YUV422 planar, YUV422 semi-planare
 YUV 10-bit pro YUV420/422 semi-planari
BPP8, BPP4, BPP2, BPP1
Destination formats:
ABGR8888, XBGR888, ARGB8888, XRGB888
RGB888, RGB565
RGBA5551, RGBA4444
 YUV420 planae, YUV420 semi-planaribus
YUV422 planar, YUV422 semi-planare
Forma conversionis Pixel, BT.601/BT.709
Max resolutio: 81928192 fons, 40964096 destination
BitBlt
Duo fontes BitBLT:
A+B=B tantum BitBLT, Firmamentum rotatum et scala B fixa
A+B=C secundo fonte (B) habet idem quod (C) plus munus gyrationis
Color replete cum CLIVUS satiata, et exemplar satiata
Summus perficientur proten ac recusare
dilatatio Monochrome pro textu reddendo
Nova comprehensive per-pixel alpha (color / alpha channel separatim)
Alpha miscent modos inter Java 2 Porter-Duff praecepta componendo miscent, chroma clavem, forma larva, evacuatur
Dither operandi
 0, 90, 180, 270-gradus gyrationis
x-speculum, y-speculum, et gyrationis operatio
Imago Processus Enhancement (IEP):
Imago forma
Input data: YUV420/YUV422, semi-plana / plani, UV swap
Output data: YUV420/YUV422, semi-planaribus, UV swap, tile modus
YUV in sampling conversionem a 422 ut 420
Max resolutio ad imaginem dynamicam usque ad 1920×1080
De-interlace
1.2.11 Propono Interface
unum usque ad 24 bits RGB parallel video output interface
One BT.1120 video output interface
One 4-lane MIPI DSI interface, ad 1Gbps per venellam
Usque ad 1080p@60fps
1.2.12 Video Output Processor (GTC)
 Usque ad 1920×1080 @60fps
Multiplex iacuit
Maecenas vitae accumsan
Win0 layer
Win2 layer
Input format: RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
 1/8 ut 8 scalas, ac scalis sursum machinam
Support virtual display
 256 alpha level mixtura (alpha multiplex auxilium pre-)
Perspicuus color key
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
YCbCr2RGB (rec601-mpeg/ rec601-jpeg/rec709)
RGB2YCbCr (BT.601/BT.709)
Support multi-regionis
Win0 iacuit et Win2 iacuit operies exchangeable
Support RGB vel YUV domain operies
BCSH (candor, contrast, Saturatio, Huc temperatio)
BCSH: YCbCr2RGB (rec601-mpeg/ rec601-jpeg/rec709)
BCSH: RGB2YCbCr (BT.601/BT.709)
Support Gamma adjust
Support dither allegro RGB888to666 RGB888to565 &amp; dither descendit FRC (configurable) RGB888to666
Blank et nigrum ostentationem
1.2.13 Audio Interface
I2S0 cum 8 ductus
Sursum to 8 channels TX and 8 vias RX iter
Audio senatus ab 16bits ad 32bits
Sample rate usque ad 192KHz
Dominus et servus modum operis providet, software configurable
Support 3 I2S formats (normalis ", left-iustus, justificatus)
Support 4 PCM formats (mane, late1, late2, late3)
I2S ac PCM modus non potest esse simul
I2S1/I2S2 with 2 ductus
Sursum to 2 channels for TX and * 2 vias RX iter
Audio senatus ab 16bits ad 32bits
Sample rate usque ad 192KHz
Dominus et servus modum operis providet, software configurable
Support 3 I2S formats (normalis ", left-iustus, justificatus)
Support 4 PCM formats (mane, late1, late2, late3)
I2S ac PCM non possunt simul
PDM
Sursum to 8 ductus
Audio senatus ab 16bits ad 24bits
Sample rate usque ad 192KHz
Support PDM dominum accipere modus
TDM
Support up to 8 channels for TX and * 8 channels for RX iter
Audio senatus ab 16bits ad 32bits
Sample rate usque ad 192KHz
Dominus et servus modum operis providet, software configurable
Support 3 I2S formats (normalis ", left-iustus, justificatus)
Support 4 PCM formats (mane, late1, late2, late3)
Audio PWM
Support convertendi PCM ad PWM format
Sample rate usque ad 16x
Suscipe interpolationem linearem pro 2x/4x/8x/16 oversampling
Support 8/9/10/11 frena maskable L / R channel PWM output
Digital Audio Codec
Support 3 channel digitale ADC
Support 2 channel digitale DAC
Support I2S/PCM interface
Support I2S / PCM dominus et servus modus
Support 4-canalem audio transmittendi in I2S modus
Support II-alveum audio recipiendi in I2S modus
Support II-alveum audio transmittendi vel recipiendi in PCM modus
Support 16~24 frenum sample resolution for both digital ADC and digital DAC
<spatium style =”color: #ffffff;”>RV1126 Datasheet Rev 1.4</spatium>
Ambo digitales ADC et digitales DAC sustinent tres coetus sample rates. Group 0 sunt 8khz/16khz/32kHz/64kHz/128khz, group 1 sunt 11.025khz/22.05khz/44.1khz/88.2khz/176.4khz et coetus 2 are 12khz/24khz/48khz/96khz/192khz
 Passband of digital ADC filters est 0,45625*fs
Support digital ADC passum-cohortem laniatus intra +/-0.1dB
Subsisto cohortis digitalis ADC Filtra est 0.5*fs
Support digital ADC stop-cohortem attenuationem saltem 60dB
Voluminis imperium subsidium tam digitalis ADC et digitalis DAC
Support Lorem Level Imperium (ALC)et sonitus porta digitalis ADC
Communicatio cum Analogo Codicis Support per I2C bus
1.2.14 connectivity
SDIO Interface
Compatible cum SDIO3.0 protocol
4bits data bus latitudines
GMAC 10/100/1000M moderatoris aetherei
 Support 10/100/1000-Mbps datae translationis rates cum RGMII interfaces
Support 10/100-Mbps data translationis rates cum RMII interfaces
Suscipe utrumque plena duplicatum et dimidium duplici operatione. Suscipe pro TCP Segmentation Offload (TSO) et UDP Segmentation Offload (USUS) network accelerationis<br>
USB 2.0 Host
Compatible cum USB 2.0 specificatio
subsidia summus celeritas(480Mbps), plena celeritate(12Mbps) et humilis celeritate(1.5Mbps) modus
Support consectetur Hostiam Controller interface Specification (EHCI), Recognitio 1.0
Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
USB 2.0 OTG
Compatible Specification
Universal Vide Bus Specification, Recognitio 2.0
Extensibilis Hostiam Controller interface pro Universali Serial bus (xHCI), Recognitio 1.1
Imperium Support / Mole / Interrumpere / Isochronum TRANSFERENDIS
SPI Interface
Support 2 SPI Controllers, support duos chip-eligere output
Suscipe Vide-Dominum et Vide-servum modum, software-configurable
I2C Interface
Support 6 I2C interfaces(I2C0-I2C5)
Support 7bits et 10bits oratio modus
Software programmable horologium frequency
Data in I2C-bus transferri potest ad rates of usque ad 100k frena / s in Latin modus, ad 400k bits / s in Fast modus, aut ad 1m bits / s in Fast-modus Plus
UART Interface
Support 6 UART interfaces (UART0-UART5)
Support 5bit, 6paulum, 7paulum, et 8bit Vide data transmittere vel recipere
Standard asynchronous communicationis frena ut satus, prohibere, et pari
Suscipe alia initus horologiorum pro UART operandi ut ad 4Mbps baud rate
Support Auto fluxus imperium modus(nisi UART2)
1.2.15 alii
Multiplices GPIO
Omnes GPIOs possunt ad generandum interruptio
Support gradu felis et in ore felis adjicias
Support configurable verticitatem gradu felis adjicias
Support configurable ortu ore, procidens in ore gladii, et utraque ora felis adjicias
Support configurable viverra directionem (et infirma viverra-sursum et infirma viverra-down)
<fortis>RV1126 Datasheet Rev 1.4</fortis>
Support configurable coegi vires
Temperature Sensor (TS-ADC)
Support User definitae Modus et Lorem Modus
In User definivit modus, start_of_conversion coerceri omnino a software, et etiam generari potest ex hardware.
In Lorem Modus, temperatus terrorem(summus / humilis temperatus) adjicias esse configurable
In Lorem Modus, ad temperatus systematis reset configurable esse potest
Support to 2 channel TS-ADC (propter CPU et NPU respectively), temperatus criteria cuiusque canalis configurable esse potest
-40~ 125°C temperatus range et 5°C temperatus resolutio
 12-bit SAR ADC up to 732 S / s sampling rate
Successive approximatio ADC (SAR ADC)
X-bit resolutio
Ad 1MS / s sampling rate
 6 una finita initus channels
OTP
Support 32Kbit spatii et altior 4k oratio spatium est non-securam partem.
Support lege et programma verbi persona in tutis exemplar
Support longitudo ex progressio 1 ut 32 paulum
Read operatio firmamentum 8bit solum
Programma et lege publica legi potest
Progressio non alloqui recordum
Package genus
 FCCSP 409-pin (corpus: 14mm x 14mm; Pila magnitudine: 0.3mm; pila picem: 0.65mm)
Notae:
①: DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 non est usus eodem tempore

RKDevTool_Release_v2.74

https://drive.google.com/file/d/19rfUc4DJP5bPmdeCoDLsawo9b8zZxKMH/view?usp=sharing

SDK

https://drive.google.com/file/d/1CCNWHNNVi8FVG6UXNgrMDYsZx3SrpFyr/view?usp=sharing

Data sheet

RV1126-Vcan1748 Data Sheet

RV1126 RV1109 Quick Start

Rockchip_RV1126_RV1109_Quick_Start_Linux_EN

Rockchip Developer Guide RockX_SDK

Rockchip_Developer_Guide_RockX_SDK_CN

Rockchip_Developer_Guide_RockX_SDK_EN

A customer asked whether our RV1126 development board has WiFi and Bluetooth functions.

Our board hardware itself does not come with WiFi and Bluetooth modules, but you can add a WiFi module through USB to realize the RV1126 board with a WiFi function. Bluetooth is not currently supported.

Another brand camera to replace Sony IMX415

Customers ask if our boards do not use the Sony IMX camera, he wants to use other brands of cameras. Bene, we need to look at the camera information, consilium, and specifications first.

Our engineers will evaluate it first. If confirmed, we need to change the camera driver on the RV1126 firmware. Bene, the camera’s driver needs to be provided by the customer. It would be best to provide us with a piece of hardware so that we can test and verify whether it can work well while modifying it.

http://youtube.com/shorts/ud8VvntMqTs